RAS Hardware Architect
il y a 1 jour
Barcelona
ph3Overview /h3 pJoin to apply for the bRAS Hardware Architect /b role at bOPENCHIP SOFTWARE TECHNOLOGIES /b /p pThe SoC Architecture team is responsible for defining high-performance and power efficient System-on-Chip hardware architecture. The team identifies Hardware Requirements, defines the overall SoC system and delivers High-level Architecture Specification (HAS) integrating multiple processing units, memory, interconnects, accelerators, interfaces and peripherals to achieve optimal Power, Performance, Area and Cost (PPAC) efficiency. The team is also responsible for overall aspects of security, debug, production test and device packaging and for defining and maintaining Configuration Management processes for scalable and configurable architectures. /p pThe team works closely with Product, Technology, Software and AI, and Hardware Engineering Teams for Design Implementation and Verification. /p h3The Role /h3 pThe ideal candidate should have strong knowledge of hardware architectures, VLSI design, and successful industry experience with deployment of IPs in large SoC while working in a collaborative environment. This is a Hardware Architecture role that emphasizes a strong focus on defining and integrating Reliability, Availability and Serviceability (RAS) requirements and features for a resilient Hardware Architecture. This role requires proactive collaboration with security experts and teams involved in Hardware Implementation, Software, System, and Product security. You will be responsible for all aspects of Hardware Security, throughout the Concept, Definition, and Specification of Hardware Architecture. /p h3Key Responsibilities /h3 ul liArchitect and define overall SoC including processing units, hardware accelerators, memory, interconnect, interfaces and analog components. /li liWork hand in hand with the product architects making sure hardware architecture meets the product goals. /li liDefine RAS strategies, support the architecture of RAS features and the intersection of RAS with all aspects of Hardware Design and Software implementation. /li liDevelopment of hardware architecture models and simulations that include RAS metrics (e.g. Failure in Time for permanent and transient errors and Architecture Vulnerability Factor (AVF)). /li liEvaluation of architectural and micro-architecture options including different levels of protection and protection mechanisms (e.g. Error Correction Code, parity, redundancy) and the impacts in Power Performance, Area and Cost (PPAC). /li liConduct system-level modelling and analysis to optimise for power, performance, area and cost. /li liWork with Software and Firmware teams for efficient and optimal system codesign. /li liEvaluate new processes, technologies, trends, and industry standards. /li liPerform hard and soft IP identification, analysis and selection. /li liLead architecture definition, reviews and provide technical guidance. /li liWork with peer micro architects across the organization aligning product and architecture definition. /li liCollaborate with design implementation, verification, physical design, software and firmware teams for development and design convergence. /li liSupport SoC execution across project milestones working with all crossfunctional teams to identify and drive complex dependencies resolution. /li liDefine and develop system-level methodologies, tools, and IPs to build SoCs in an efficient and scalable manner. /li liThis role requires a talent for cross-functional collaboration, where effective communication and engagement are essential throughout the entire Product Development process, with a strong emphasis on reliability. /li /ul h3Qualifications /h3 ul liBachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering or related field; 10+ years of solid experience in IP/SoC architecture and design for ASIC or FPGA. /li liFoundational understanding and familiarity with key reliability themes is desired, including: Error detection and correction codes as ECC, CRC, parity, Reed-Solomon, BCH. /li liFault isolation, failover, redundancy mechanisms (spare cores, redundant memory channels, retry logic, watchdog timers). /li liFamiliarity with serviceability features such as logging, telemetry, and predictive failure analysis. /li liExperience with thermal, voltage, and aging-related failures. /li liGood knowledge on Design for Testability and Manufacturability and the intersection with RAS. /li liExperience with architecture trade-offs and design methodologies for optimal performance power area cost (PPAC) in advanced technologies. /li liProficiency in performance modelling, simulation frameworks and scripting. /li liStrong knowledge and industry expertise in multiple aspects of SoC architecture definition such as Clocks, Resets, Power-Sequencing, Power Management, Interrupts, Interconnects, Boot, Virtualization, Security, System Performance, IO technologies, Platform integration. /li liExperience with RISC-V based Systems. /li liGeneral knowledge of SoC implementation standards, interconnect (AMBA, AXI, CHI) and interfaces (PCIe, UCIe, I2C, I3C, SPI, JTAG). /li liGeneral knowledge of Advanced packaging (2.5D, 3D, SiP, CoWoS) and chiplets. /li /ul h3What do we offer? /h3 ul liJoin an innovative team and experience company growth. /li liWe believe in investing in our employees and providing them with the opportunities they need to grow and develop their careers. /li liEnjoy a hybrid work environment. /li liWe also offer flexible schedule. /li liWe offer a remuneration that values your experience. /li liThe position will be based in Barcelona. /li /ul pWe are looking for outstanding people willing to join our mission to change this industry and help to build a better world. If you feel identified with Openchip, please contact us. We can offer a competitive compensation package in a flexible work schema that will help you to keep a balance between your personal and professional life. At Openchip Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity. /p pSeniority level: Mid-Senior level /p pEmployment type: Full-time /p pJob function: Engineering and Information Technology /p pIndustries: Software Development /p pReferrals increase your chances of interviewing at OPENCHIP SOFTWARE TECHNOLOGIES by 2x /p pSign in to set job alerts for “Hardware Architect” roles. /p pBarcelona, Catalonia, Spain /p pSant Just Desvern, Catalonia, Spain /p pBaix Llobregat, Catalonia, Spain /p pWe’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI. /p /p #J-18808-Ljbffr
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